Low power master-slave flip-flop

ABSTRACT

A flip-flop circuit may include a master latch and a slave latch. Each latch may have a transparent mode and a storage mode. The slave latch may be in storage mode when the master latch is in transparent mode; and vice-versa. A clock signal may control the mode of each latch through a pair of clock-gated pull-up transistors and a pair clock-gated of pull-down transistors, for a total of four clock-gated transistors. The clock-gated transistors may be shared by the master latch and the slave latch. Fewer clock-gated transistors may be required when they are shared, as opposed to not being shared. Clock-gated transistors may have parasitic capacitance and consume power when subjected to a varying clock signal, due to the charging and discharging of the parasitic capacitance. Having fewer clock-gated transistors thus may reduce the power consumed by the flip-flop circuit.

FIELD OF TECHNOLOGY

This disclosure relates generally to data processing devices and, more particularly, to a method, a device and/or a system of reducing the power requirement of a master-slave flip-flop circuit.

BACKGROUND

Flip-flops are storage elements used for pipelining and storing the state of a circuit. They are fundamental building blocks for sequential logic and may be controlled by a clock signal. Clock signals may be cyclical and toggle up and down between high and low voltages each cycle. On each rising edge of the clock signal, the flip-flop may accept a new data input state and propagate it to the output. Unless the clock signal is gated, each flip-flop within a circuit may be exposed to the up and down toggling of the clock during each clock cycle. A flip-flop may have parasitic capacitance, that is, unwanted capacitance that is not intentionally designed into a circuit, but merely results as an inherent property of the circuit or sub-components within a circuit. Exposure to the toggling clock signal may cause the parasitic capacitance of a flip-flop to charge and discharge. The charging and discharging of the parasitic capacitance within a flip-flop may consume power, whether or not the input data has changed state from the previous clock cycle. Since flip-flops are the most commonly used sequential logic storage cell in integrated circuits, the power consumed due to parasitic capacitance may represent a large portion of the power consumption of an integrated circuit.

SUMMARY

Disclosed are a method, a device and/or a system of a low power master-slave flip-flop.

In one aspect, a flip-flop circuit may include a master latch circuit configured to accept an input signal when a clock signal is at a first level and to hold a previous input signal when the clock is at a second level. The device may also include a slave latch circuit configured to accept an output signal from the master latch circuit when the clock signal is at the second level and to hold a previous output of the master latch circuit when the clock signal is at the first level. Further, the device may include a pull-up logic circuit configured to allow the master latch circuit to be coupled to a supply voltage when the clock signal is at the first level, and to allow the slave latch circuit to be coupled to the supply voltage when the clock signal is at the first level, with both the master latch circuit and the slave latch circuit coupled to the supply voltage through the same pull-up logic circuit.

In another aspect, a flip-flop circuit may comprise a clocked pull-up component having a first clock gated transistor coupled to a supply voltage, a second clock gated transistor coupled to the supply voltage, and a master latch component configured to propagate a level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node. The master latch component may be configured to allow the embedded logic function values of the data input bundle to propagate to the master true storage node and master complement storage node when a clock signal is at a first level, and to hold previous values of the master true storage node and the master complement storage node when the clock signal is at a second level. The master latch circuit may comprise a complement pull-up logic cone configured to generate a complement level of the embedded logic function of the data input bundle, and coupled between the first clock gated transistor and the master complement storage node. The master latch circuit may further comprise a true pull-up logic cone configured to generate a true level of the embedded logic function of the data input bundle, and coupled between the second gated transistor and the master true storage node. The flip-flop circuit may also include a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value. The slave complement storage node may be communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock is at the second level, so that the slave complement storage node retains a previous value. The slave latch component may comprise a transistor gated by the slave true storage node, coupled between the first clock gated transistors and the slave complement storage node. The slave latch component may also comprise a transistor gated by the slave complement storage node, coupled to the second clock gated transistor and the slave true storage node.

In another aspect, a flip-flop circuit may comprise a clocked pull-down component having a first clock gated pull-down transistor, coupled to a ground voltage, and a second clock gated pull-down transistor, coupled to the ground voltage, and a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node. The master latch component may be configured to allow the data input enabled logic function value and its complement to propagate to the master true storage node and master complement storage node respectively when a clock signal is at a first level, and to hold previous values of the master true storage node and the master complement storage node when the clock signal is at a second level. The master latch component may comprise a complement pull-down logic cone configured to generate a complement level of the embedded logic function of the data input bundle, coupled between the first clock gated pull-down transistor and the master complement storage node, and a true pull-down logic cone configured to generate a true level of the embedded logic function of the data input bundle, coupled between the second clock gated pull-down transistor and the master true storage node. The flip-flop circuit may also comprise a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value, and with the slave complement storage node communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock signal is a the first level, so that the slave complement storage node retains a previous value. The slave latch component may comprise a transistor gated by the slave true storage node, coupled between the first clock gated pull-down transistor and the slave complement storage node, and a transistor gated by the slave complement storage node, coupled between the second clock gated pull-down transistor and the slave true storage node.

In another aspect, a flip-flop circuit may comprise a clocked pull-up component having a first clock gated transistor coupled to a supply voltage, a second clock gated transistor coupled to the supply voltage, and a master latch component configured to propagate a level of a data input signal to a master true storage node, and a complement of the level of the data input signal to a master complement storage node. The master latch component may be configured to allow the data input signal value and its complement to propagate to the master true storage node and master complement storage node respectively when a clock signal is at a first level, and to hold previous values of the master true storage node and the master complement storage node when the clock signal is at a second level. The master latch circuit may comprise a transistor gated by a true level of the data input signal, and coupled between the first clock gated transistor and the master complement storage node. The master latch circuit may further comprise a transistor gated by a complement level of the data input signal, and coupled between the second gated transistor and the master true storage node. The flip-flop circuit may also include a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value. The slave complement storage node may be communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock is at the second level, so that the slave complement storage node retains a previous value. The slave latch component may comprise a transistor gated by the slave true storage node, coupled between the first clock gated transistors and the slave complement storage node. The slave latch component may also comprise a transistor gated by the slave complement storage node, coupled to the second clock gated transistor and the slave true storage node.

In another aspect, a system to implement a flip-flop may include a clocked pull-up component comprising a first clock gated pull-up transistor, coupled to a supply voltage, and a second clock gated pull-up transistor, coupled to the supply voltage. The system may further include a master latch component configured to propagate a true level of a data input signal to a master true storage node, and a complement of the level of the data input signal to a master complement storage node when a clock signal is at a first level, and to hold a first value of the master true storage node and hold a second value of the master complement storage node constant when a clock signal is at a second level. The master latch component may comprise a complement pull-up logic cone, configured to generate a complement embedded logic function by passing a high voltage based on a level of the data input signal, coupled between the first clock gated pull-up transistor and the master component storage node, and a true pull-up logic cone, configured to generate a true embedded logic function by passing a high voltage based on a level of the data input signal, coupled between the second clock gated pull-up transistor and the master true storage node. The system may further comprise a slave latch component having a slave true storage node and a slave complement storage node, configured so that the slave true storage node is communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value, and configured so that the slave complement storage node is communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock signal is at the first level, so that the slave complement storage node retains a previous value. The slave latch component may further comprise a transistor gated by the slave true storage node, coupled between the first clock gated pull-up transistor and the slave complement storage node, and a transistor gated by the slave complement storage node, coupled between the second clock gated pull-up transistor and the slave true storage node.

In another aspect, a flip-flop circuit may include a clocked pull-up component having a first clock gated PMOS transistor coupled to a supply voltage, a second clock gated PMOS transistor coupled to the supply voltage, and a master latch component configured to propagate a level of a data input signal to a master true storage node, and a complement of the level of the data input signal to a master complement storage node. The master latch component may be configured to allow the data input signal values to propagate to the master true storage node and master complement storage node when a clock signal is low, and to hold previous values of the master true storage node and the master complement storage node when the clock signal is high. The master latch circuit may comprise a PMOS transistor gated by a true level of the data input signal, and coupled between the first clock gated PMOS transistor and the master complement storage node. The master latch circuit may further comprise a PMOS transistor gated by a complement level of the data input signal, and coupled between the second gated PMOS transistor and the master true storage node. The flip-flop circuit may also include a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is high, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is low, so that the slave true storage node retains a previous value. The slave complement storage node may be communicatively coupled to the master complement storage node when the clock signal is high, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock is low, so that the slave complement storage node retains a previous value. The slave latch component may comprise a PMOS transistor gated by the slave true storage node, coupled between the first clock gated PMOS transistors and the slave complement storage node. The slave latch component may also comprise a PMOS transistor gated by the slave complement storage node, coupled to the second clock gated PMOS transistor and the slave true storage node.

In another aspect, a flip-flop circuit includes a clocked pull-down component having a first clock gated NMOS transistors coupled to a ground, and a second clock gated NMOS transistor coupled to the ground, and a master latch component configured to propagate a level of a data input signal to a master true storage node, and a complement of the level of the data input signal to a master complement storage node. The master latch component may be configured to allow the data input signal values to propagate to the master true storage node and master complement storage node when a clock signal is high, and to hold previous values of the master true storage node and the master complement storage node when the clock signal is low. The master latch circuit may comprise a NMOS transistor gated by a true level of the data input signal, and coupled between the first clock gated NMOS transistor and the master complement storage node. The master latch circuit may further comprise a NMOS transistor gated by a complement level of the data input signal, and coupled between the second clock gated NMOS transistor and the master true storage node. The flip-flop circuit may also include a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is low, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is high, so that the slave true storage node retains a previous value. The slave complement storage node may be communicatively coupled to the master complement storage node when the clock signal is low, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock is high, so that the slave complement storage node retains a previous value. The slave latch component may comprise a NMOS transistor gated by the slave true storage node, coupled between the first clock gated NMOS transistor and the slave complement storage node. The slave latch component may also comprise a NMOS transistor gated by the slave complement storage node, coupled to the second clock gated NMOS transistors and the slave true storage node.

The methods and systems disclosed herein may be implemented in any means for achieving various aspects, and may be executed in a form of a non-transitory machine-readable medium embodying a set of instructions that, when executed by a machine, cause the machine to perform any of the operations disclosed herein. Other features would be apparent from the accompanying drawings and from the detailed description that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of this invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 is a block diagram of a low power master-slave flip-flop, according to one or more embodiments.

FIG. 2 is a circuit diagram of a low power master-slave flip-flop having two clocked PMOS pull-up transistors and two clocked NMOS pull-down transistors, according to one or more embodiments.

FIG. 3 is a circuit diagram of a low power master-slave flip-flop having two fewer un-clocked PMOS pull-up transistors and alternative n-keeper connections, according to one or more embodiments.

FIG. 4 is a circuit diagram of a low power master-slave flip-flop having a connection between two clocked NMOS pull-down transistors and two nodes in the master latch circuit, according to one or more embodiments.

FIG. 5 is a process flow diagram of a low power master-slave flip-flop, according to one or more embodiments.

FIG. 6 is a high level diagram of a low power master-slave flip-flop with embedded logic function having true pull-up logic, complement pull-up logic, true pull-down logic, and complement pull-down logic.

Other features of the present embodiments would be apparent from the accompanying drawings and from the detailed description that follows.

DETAILED DESCRIPTION

Example embodiments, as described below, may be used to provide a method, a system and/or a device for implementing a low power master-slave flip-flop.

FIG. 1 shows, according to one or more embodiments, a block diagram of a low power master-slave flip-flop (LPMSFF) 100. In one or more embodiments, LPMSFF 100 may comprise a master latch circuit 110 communicatively coupled to a data input signal D 105. In one or more embodiments, D 105 may represent a digital value, such as 0, 1, high, low, on, off, true, false, etc. As used herein, a “level” of a digital value may be used synonymously with a “state” of a digital value. In one or more embodiments, LPMSFF 100 may comprise a pull-up logic circuit 102 and a pull-down logic circuit 104. Pull-up logic circuit 102 and pull-down logic 104 circuit may be communicatively coupled to clock signal CP 130. CP 130 may be a periodic square-wave signal, alternating between high and low states, and having rising and falling edges. Pull-up logic circuit 102 may be configured to allow a connection to a supply voltage during a given state of CP 130, and/or a given transition between states of CP 130. Pull-down logic circuit 104 may be configured to allow a connection to a ground during a given state of CP 130, and/or a given transition between states of CP 130. For example, pull-up logic circuit 102 may allow a connection to supply voltage when CP 130 is in a high state (1), and/or pull-down logic circuit 104 may allow a connection to ground when CP 130 is in a low state (0).

FIG. 1 also shows, according to one or more embodiments, master latch circuit 110 (which may also be referred to as a master latch component) communicatively coupled to pull-up logic circuit 102, and/or optionally, master latch circuit 110 communicatively coupled to pull-down logic circuit 104. In one embodiment, master latch circuit 110 may have a transparent mode and/or a storage mode. In the transparent mode, according to one or more embodiments, master latch circuit 110 may be enabled to accept a new input from D 105 when CP 130 is in a particular state, and/or when CP 130 transitions from one state to another state. In a storage mode, according to one or more embodiment, master latch circuit 110 may be configured so that it does not accept a new input from D 105, but maintains, in storage, a value previously accepted from D 105, and outputs the previously accepted and stored value of D 105 through a master true storage node m 112. In one or more embodiments, master latch circuit 110 may output a complement of the aforementioned previously stored value of D 105 through a master complement storage node mN 114, when in storage mode. Master latch circuit 110 may be in a storage mode when CP 130 is in a complement state to the state in which master latch circuit 110 would be enabled to be in transparent mode. For example, master latch circuit 110 may be in a transparent mode when CP 130 is in a low state (0), and master latch circuit 110 may be in a storage mode when CP 130 is in a high state (1), or vice-versa.

In one or more embodiments, according to FIG. 1, CP 130 may indirectly control whether master latch circuit 110 is in transparent mode or storage mode through pull-up logic circuit 102 and/or pull-down logic circuit 104. For example, when CP 130 is in a low state (0), it may enable pull-up logic circuit 102 to connect to a supply voltage, pull-up logic circuit 102 may in turn supply power to a portion of master latch circuit 110, thus enabling master latch circuit 110 to accept a new input value of D 105, and placing master latch circuit 110 in transparent mode.

FIG. 1 further shows, according to one or more embodiments, slave latch circuit 120 (which may also be referred to as a slave latch component). In one or more embodiments, slave latch circuit 120 may be communicatively coupled to master latch circuit 110, pull-up logic circuit 102, and pull-down logic circuit 104. Slave latch circuit 120 may be communicatively coupled with master latch circuit 110 through m 112 and/or mN 114. In one or more embodiment, slave latch circuit 120 may have a transparent mode and/or a storage mode. In a transparent mode, according to one or more embodiment, slave latch circuit 120 may be enabled to accept a new input from master latch circuit 110 through m 112 and/or mN 114 when CP 130 is in a particular state, and/or when CP 130 transitions from one state to another state. In storage mode, according to one or more embodiment, slave latch circuit 120 may be configured so that it does not accept a new input from master latch circuit 110, but maintains, in storage, a value previously accepted from master latch circuit 110, through m 112 and/or mN 114; and may output the value previously stored in slave latch circuit 120 through output signal Q 140. Slave latch circuit 120 may be in a storage mode when CP 130 is in a complement state to the state in which the slave latch circuit 120 would be enabled to be in transparent mode. For example, slave latch circuit 120 may be in a transparent mode when CP 130 is in a high state (1), and slave latch circuit 120 may be in a storage mode when CP 130 is in a low state (0), or vice-versa.

In one or more embodiments, according to FIG. 1, CP 130 may indirectly control whether slave latch circuit 120 is in transparent mode or storage mode through pull-up logic circuit 102 and/or pull-down logic circuit 104. For example, when CP 130 is in a high state (1), it may enable pull-down logic circuit 104 to connect to ground, pull-down logic circuit 104 may in turn allow a portion of slave latch circuit 120 to connect to ground, thus enabling slave latch circuit 120 to accept a new input from master latch circuit 110, through m 112 and/or mN 114, thereby placing the slave latch circuit 120 into transparent mode, and propagating the value of input m 112 to output Q 140.

According to one or more embodiments, pull-up logic circuit 102 may comprise one or more circuit elements. Pull-down logic circuit 104, according to one or more embodiments, may comprise one or more circuit elements. In one or more embodiments, a circuit element which may be included in pull-up logic circuit 102 and/or pull-down logic circuit 104 may be a transistor. Electronic circuit elements, including transistors, may have parasitic capacitance. Parasitic capacitance of a circuit element may be unwanted capacitance that is not intentionally designed into the circuit element, but merely results as an inherent property of the circuit element. In one or more embodiments, CP 130 may alternate between a high voltage value and a low voltage value, which may expose a circuit element in pull-up logic circuit 102, and/or a circuit element in pull-down logic circuit 104 to voltage that may alternate between a high and low value. The aforementioned exposure to voltage that may alternate between a high and low value may cause the parasitic capacitance of a circuit element in pull-up logic circuit 102, and/or a circuit element in pull-down logic circuit 104, to alternately charge and discharge. In one or more embodiments, the aforementioned charging and discharging of the parasitic capacitance of a circuit element in pull-up logic circuit 102 and/or pull-down logic circuit 104 may result in parasitic power consumption, by a flip-flop, with each high/low cycle of CP 130, whether or not any other input or output value associated with the flip-flop changes during the same cycle of CP 130. In one or more embodiments, pull-up logic 102 and/or pull-down logic 104 may be shared by both master latch circuit 110 and slave latch circuit 120. In one or more embodiments, the aforementioned sharing may reduce the total number of circuit elements which may be exposed to high/low cycles of CP 130, which in turn may reduce the parasitic power loss due to parasitic capacitance, and thus the total power consumption of a LPMSFF, to a level below the power consumption of a flip-flop in which pull-up logic circuit 102 and/or pull-down logic circuit 104 were not shared by master latch circuit 110 and slave latch circuit 120.

In one or more embodiments, multiple LPMSFFs may be connected to each other. For example, the output Q 140 from a first LPMSFF may be used as input D 105 for a second LPMSFF.

The exemplary embodiments shown in FIGS. 2, 3, 4, and 6, are illustrated using complementary metal-oxide-semiconductor (CMOS) technology. CMOS technology may employ complementary and symmetrical n-type metal-oxide-semiconductors (NMOS) and p-type metal-oxide-semiconductors (PMOS). In one or more embodiments, as exemplified in FIGS. 2, 3, 4, and 6; the LPMSFF may be configured so that the propagation of new data state to output shown occurs at a rising edge of a clock signal. Other forms of the LPMSFF may be appreciated by one of ordinary skill in the art and are within the scope of the exemplary embodiments discussed herein. For example, one of ordinary skill in the art would appreciate that alternative embodiments, configured so that the propagation of new data state to output may occur at a falling edge of a clock signal, may be implemented by exchanging the PMOS transistors shown with NMOS transistors, exchanging the NMOS transistors shown with PMOS transistors, exchanging supply voltage with a ground voltage, and exchanging ground with supply voltage. In one or more embodiments, a master-slave flip-flop which transfers a new state of data to output at a rising edge may be a positive edge flip-flop, with a positive edge being a transition between a first level of the clock and a second level of the clock, wherein the first level of the clock may be a low level of the clock and the second level of the clock may be a high level of the clock. In one or more embodiments, a master-slave flip-flop which transfers a new state of data to output at a falling edge may be a negative edge flip-flop, with a negative edge being a transition between a first level of the clock and a second level of the clock, wherein the first level of the clock may be a high level of the clock and the second level of the clock may be a low level of the clock.

FIG. 2 shows, according to one or more embodiments, a LPMSFF. In one or more embodiments, LPMSFF may have twelve PMOS transistors (202, 204, 210, 212, 218, 220, 222, 224, 234, 236, 240, 242), may have twelve NMOS transistors (206, 208, 214, 216, 226, 228, 230, 232, 244, 246, 248, 250), and may have two inverters (260, 262). An inverter may comprise two transistors. A transistor may have three nodes; a source, a gate and a drain. An NMOS transistor may be configured to allow current to flow between the source node and the drain node when the gate node is connected to high voltage or 1. A PMOS transistor may be configured to allow current to flow between the source node and the drain node when the gate node is connected to low voltage or 0. When a transistor is in a state in which it allows current flow between its source node and its drain node, it may be said to be ON, and it may be said to be OFF otherwise. A transistor may be said to be “switched” ON/OFF at its gate node, or, synonymously, “gated” ON/OFF at its gate node. An inverter may have an input node and an output node, with the inverter configured to produce an output that is the complement of the signal at the input node. For example, an inverter may accept a high, or 1, as input, and then send a low or 0 as output; or, an inverter may accept a low, or 0, as input, and then send a high or 1 as output. An inverter may be constructed from one or more transistors. In one or more embodiments, clock signal CP 130 may cycle between high and low values, or states, with a high value representing a 1, and a low value representing a 0.

In one or more embodiments, as shown in FIG. 2, master latch circuit 110 may comprise transistors (204, 206, 212, 214), with the aforementioned transistors configured as cross-coupled inverters to form a storage circuit. In one or more embodiments, master latch circuit 110 may also comprise transistors (230, 248). In one or more embodiments, slave latch circuit 120 may comprise transistors (222, 224, 240, 242), with the aforementioned transistors configured as cross-coupled inverters to form a storage circuit. In one or more embodiments, pull-up logic circuit 102 may comprise one or more transistors, with the aforementioned one or more transistors configured to enable a connection to a supply voltage. In one example, as shown in FIG. 2, pull-up logic circuit 102 may comprise transistor 218 and transistor 234. Transistors (218, 234) may be switched between ON and OFF states by the clock signal CP 130. Transistors that may be switched between ON and OFF states by the clock signal CP 130 are clocked or clock-gated transistors. Transistors that may not be directly switched between ON and OFF states by CP 130 are un-clocked transistors. In one or more embodiments, pull-down logic circuit 104 may comprise one or more transistors, with the aforementioned transistors configured to enable a connection to a ground. In one example, as shown in FIG. 2, pull-down logic circuit 104 may comprise transistor 232 and transistor 250. Transistors (232, 250) may be switched between ON and OFF states by the clock signal CP 130.

In one or more embodiments, according to FIG. 2, transistors (202, 208) may be switched/gated by D 105; and transistors (210, 216) may be switched/gated by dN 270. In one or more embodiments, transistors (204, 206, 230, 240, 246) may be switched/gated by m 112; and transistors (212, 214, 222, 226, 248) may be switched/gated by mN114. In one or more embodiments, transistors (236, 242, 244) may be switched/gated by a slave true storage node s 275; and transistors (220, 224, 228) may be switched/gated by a slave complement storage node sN 280.

In one or more embodiments, according to FIG. 2, if CP 130 is equal to 1, then transistors (218, 234) are OFF, and transistors (232, 250) are ON. In one or more embodiments, input D 105 may have a digital value of high, low, on, off, true, false, 0, 1, etc. In one or more embodiments, if CP 130 is equal to 1 and D 105 is equal to 1, the transistor 202 would be OFF and transistor 208 would be ON. In one or more embodiments, if D 105 is equal to 1, it may pass through invertor 260 resulting in dN 270 having the complementary value of 0. If dN 270 is equal to 0, then transistor 210 would be ON and transistor 216 would be OFF.

If, according to one or more embodiments, m 112 is initially equal to 1, then transistor 206 would be ON and transistor 204 would be OFF; this will connect mN 114 to the ground through transistor 206 and transistor 208. If mN 114 is connected to ground, it would be forced to have a low voltage and be equal to 0. If mN 114 is equal to 0, then transistor 212 would be ON and transistor 214 would be OFF; therefore, m 112 would be connected to supply voltage through transistor 212, and would remain at high voltage and equal to 1.

If, according to one embodiment, CP 130 is equal 1, D 105 is equal to 1, and m 112 is initially equal to 0, then transistor 204 would be ON and transistor 206 would be OFF; therefore mN 114 would be connected to supply voltage through transistor 204 and mN 114 would be equal to 1. If mN 114 were equal to 1, then transistor 212 would be OFF and transistor 214 would be ON; which would cause m 112 to be connected to ground through transistor 214 and transistor 216; therefore the value of m 112 would be low, or 0, and m 112 would retain its initial value.

If, according to one embodiment, CP 130 is equal to 1, and D 105 is equal to 0; then transistor 202 would be ON and transistor 208 would be OFF. Because dN 270 is equal to the complement of D 105, due to inverter 206, dN 270 would be equal to 1, which would cause transistor 210 to be OFF and transistor 216 to be ON. Changing the value of D from 1 to 0, when CP 130 is equal to 1, does not affect the value of m 112 or mN 114, in one or more embodiments, because the values of m 112 and mN 114 are not affected by any of the transistors that D 105 or dN 270 switch ON/OFF (i.e. 202, 208, 210, 216).

In summary, according to one or more embodiments, as shown in FIG. 2, if CP 130 is equal to 1, m 112 and mN 114 retain their initial values, regardless of the value of D 105.

According to one or more embodiments, as shown in FIG. 2, if CP 130 is equal to 0, then transistor 218 and transistor 234 would be ON, and transistor 232 and transistor 250 would be OFF. Therefore, cpv0 285 and cpv1 290 would be connected to supply voltage and both be equal to 1.

If, in one or more embodiments, CP 130 is equal to 1 and D 105 is also equal to 1, then dN 270 would be equal to 0, because dN 270 is the complement of D 105 due to inverter 260. If D 130 is equal to 1, then transistor 202 would be OFF and transistor 208 would be ON. If dN 270 is equal to 0, then transistor 216 would be OFF and transistor 210 would be ON. Therefore, in one or more embodiments, m 112 would be connected to supply voltage through transistor 210 and transistor 218, so that m 112 would be set equal to 1, regardless of its initial value. If m 112 is equal to 1, then transistor 204 would be OFF, and transistor 206 would be ON; causing mN 114 to be connected to ground through transistor 206 and transistor 208, therefore mN 114 would be set low and equal to 0, regardless of the initial value of mN 114. If mN 114 is equal to 0, then transistor 212 would be ON and transistor 214 would be OFF; therefore m 112 would also be connected to supply voltage through transistor 212, as well as through transistors (210, 218).

If, according to one or more embodiments, as represented by FIG. 2, CP 130 is equal to 0 and D 105 is also equal to 0, then dN 270 would be equal to 1, due to inverter 260; and transistor 202 would be ON, transistor 208 would be OFF, transistor 216 would be ON, and transistor 210 would be OFF. In one or more embodiments, with transistors 202 and 216 ON, mN 114 would be connected to supply voltage through transistor 202 and transistor 234; therefore, mN 114 would be set high, and equal to 1, regardless of its initial value. If mN 114 is equal to 1, then transistor 214 would be ON and transistor 212 would be OFF, connecting m 112 to ground through transistor 214 and transistor 216; so that m 112 would be set low, and equal to 0, regardless of the initial value of m 112. With m 112 equal to 0, transistor 204 would be ON and transistor 206 would be OFF, so that mN 114 would be connected to supply voltage through transistor 204 as well as through transistors 202 and 234.

In summary, in one or more embodiments, for the master latch circuit 110, if CP 130 is equal to 0, the m 112 would be set equal to the value of D 105, and mN 114 would be set equal to the complement of m 112; if, however, CP 130 is equal to 1, then both m 112 and mN 114 would retain their initial values, regardless of the value of D 105.

FIG. 2 also shows, according to one or more embodiments, that if CP 130 is equal to 0, then transistor 218 and transistor 234 would be ON, transistor 234 and transistor 250 would be OFF; therefore a node cpv0 285 would be connected to supply voltage through transistor 218, a node cpv1 290 would be connected to supply voltage through transistor 234, and both cpv0 285 and cpv1 290 would be equal to 1. In one or more embodiments, as described above, if CP 130 is equal to 0, then m 112 would be set equal to the value of D 105. If CP 130 is equal to 0, and D 105 is equal to 1, then dN 270 would be equal to 0 (the complement of D 105, due to inverter 260), m 112 would be set equal to 1, and mN 114, the complement of m 112, would be set equal to 0. If D 105 is equal to 1 and dN 270 is equal to 0, then transistor 202 would be OFF, transistor 208 would be ON, transistor 216 would be OFF, and transistor 210 would be ON. If, in addition to D 105 being equal to 1, m 112 is equal to 1, then mN 114 would be equal to 0, and transistor 240 would be OFF, transistor 246 would be ON, transistor 230 would be ON, transistor 222 would be ON, transistor 226 would be OFF, and transistor 248 would be OFF.

Under the aforementioned conditions, according to one or more embodiments, if, in addition to CP 130 being equal to 0 and D 105 being equal to 1, the initial value of the slave true storage node s 275 is equal to 1, then transistor 236 would be OFF, transistor 242 would be OFF, and transistor 244 would be ON. Therefore, the slave complement storage node sN 280 would be connected to ground through transistor 244, so that sN 280 would be equal to 0. If sN 280 were equal to 0, then transistor 220 would be ON, transistor 224 would be ON, and transistor 228 would be OFF. Therefore, s 275 would be connected to supply voltage through transistors 218, 220; as well as through transistors (224, 222); so that s 275 would retain its initial value of 1.

If, according to one or more embodiments, in addition to CP 130 being equal to 0, and D 105 being equal to 1, the initial value of s 275 is equal to 0; then transistor 236 would be ON, transistor 242 would be ON, and transistor 244 would be OFF. Therefore, sN 280 would be connected to supply voltage through transistors 236, 234; and so sN 280 would be set high, and equal to 1, regardless of the initial value of sN 280. If sN 280 is equal to 1, then transistor 220 and transistor 222 would be OFF, and transistor 228 would be ON, which would cause s 275 to be connected to ground through transistor 228, so that s 275 would be equal to 0; thus s 275 would retain its initial value. So, if CP 130 is equal to 0, and D 105 is equal to 1; s 275 will retain its initial value; that is, s 275 will not be set to the value stored as m 112 in the master latch circuit 110. If s 275 retains its initial value, then Q 140 would also retain its original value; because Q 140 is indirectly equal to s 275; due to Q 140 being equal to the complement of sN 280, because of the value of sN 280 passing through inverter 262; and sN 280 is equal to the complement of s 275, so that Q=sN′=s. (The prime symbol “′” may be used to indicate a complement, e.g. if s 275 were equal to 1, then s′ would be equal to 0, and, therefore, the complement sN would be equal to s′.)

FIG. 2 also shows that, according to one or more embodiments, if CP 130 is equal to 0, m 112 would be set equal to D 105, as described above. If, for example, CP 130 is equal to 0 and D 105 is equal to 0, then dN 270 would be equal to 1 (the complement of D 105, due to inverter 260), m 112 would be set equal to 0, and mN 114, the complement of m 112, would be set equal to 1. Under the aforementioned conditions, in one or more embodiments, transistor 218 would be ON, transistor 234 would be ON, transistor 232 would be OFF, transistor 250 would be OFF, transistor 202 would be ON, transistor 208 would be OFF, transistor 216 would be ON, transistor 210 would be OFF, transistor 240 would be ON, transistor 246 would be OFF, transistor 230 would be OFF, transistor 222 would be ON, transistor 220 would be ON, and transistor 248 would be OFF.

In one or more embodiments, with transistors (218, 234, 202, 216, 240, 222, 220) ON, and transistors (232, 250, 208, 210, 246, 230, 248) OFF; if the initial value of s 275 is equal to 1, then transistor 236 would be OFF, transistor 242 would be OFF, and transistor 244 would be ON. Therefore, sN 280 would be connected to ground through transistor 244, so that sN 280 would be low and equal to 0. If sN 280 were equal to 0, then transistor 220 would be ON, transistor 224 would be ON, and transistor 228 would be OFF. So, s 275 would be connected to supply voltage through transistors (218, 220), and through transistors (224, 222); and therefore s 275 would retain its initial value of 1.

In one or more embodiments, with transistors (218, 234, 202, 216, 240, 222, 220) ON, and transistors (232, 250, 208, 210, 246, 230, 248) OFF; if the initial value of s 275 is equal to 0, then transistor 236 would be ON, transistor 242 would be ON, and transistor 244 would be OFF. Therefore, sN 280 would be connected to supply voltage through transistors (236, 234), so that sN 280 would be equal to 1, regardless of the initial value of sN 280. If sN 280 were equal to 1, then transistor 222 would be OFF, transistor 222 would be OFF, and transistor 228 would be ON. So, s 275 would be connected to ground through transistor 228, and s 275 would retain its initial value of 0.

In summary, in one or more embodiments, for the slave latch circuit 120, if CP 130 is equal to 0, s 275, sN 280, and, therefore Q 140, will retain their initial values, regardless of the values of D 105, m 112, or mN 114.

If, in one or more embodiments, according to FIG. 2, CP 130 is equal to 1, then, transistor 232 would be ON, transistor 250 would be ON, transistor 218 would be OFF, and transistor 234 would be OFF. Also, if CP 130 is equal to 1, as shown above, m 112 and mN 114 will retain their initial values, regardless of the value of D 105. If the initial value of m 112 is 1, then transistor 240 would be OFF, transistor 246 would be ON, and transistor 230 would be ON. If m 112 is equal to 1, its complement, mN 114 would be equal to 0. With mN 114 equal to 0, transistor 222 would be ON, transistor 230 would be OFF, and transistor 248 would be OFF. With transistors (246, 250) ON, sN 280 would be connected to ground through transistors (246, 250), and would therefore be set low, and equal to 0, regardless of the initial value of sN 280. If sn 280 is equal to 0, then transistor 220 would be ON, transistor 224 would be ON, and transistor 228 would be OFF. Therefore, s 275 would be connected to supply voltage through transistors (224, 222), so that s 275 would be set equal to 1, regardless of the initial value of s 275. Therefore, Q 140 would also be set equal to 1, regardless of the initial value of Q 140, because Q=sN′ (due to inverter 262), and sN′=s, so that Q=sN′=s.

If, in one or more embodiments, as shown in FIG. 2, CP 130 is equal to 1, then, transistor 232 would be ON, transistor 250 would be ON, transistor 218 would be OFF, and transistor 234 would be OFF. If, in addition to CP 130 being equal to 1, m 112 is initially 0, then transistor 240 would be ON, transistor 246 would be OFF, and transistor 230 would be OFF. With m 112 equal to 1, its complement, mN 114, would be equal to 0, which would set transistor 222 to OFF, transistor 226 ON, and transistor 248 ON. Therefore, s 275 would be connected to ground through transistors (226, 232), and s 275 would be set low, and equal to 0, regardless of the initial value of s 275. Therefore Q 140 would also be set equal to 0, regardless of the initial value of Q 140, because Q=sN′ (due to inverter 262), and sN′=s, so that Q=sN′=s.

In summary, in one or more embodiments, as shown in FIG. 2, if CP 130 is equal to 1, then the value of s 275, and therefore the value of Q 140, would be set equal to the value of m 112.

The above operations of an exemplary embodiment as shown in FIG. 2 may be summarized in tabular form, as shown below.

SUMMARY OF OPERATIONS FOR AN EXEMPLARY EMBODIMENT OF A LOW POWER MASTER-SLAVE FLIP-FLOP CP s 275 (and Q 130 m 112 mN 114 140) sN 280 0 m would be set mN would be set s (and therefore sN will retain its equal to D 105 equal to dN 270 Q) will retain its initial value initial value 1 m will retain its mN will retain its s (and therefore sN would be set initial value initial value Q) would be set equal to mN 114 equal to m 112

FIG. 2 further shows, according to one or more embodiments, that D 105 may switch transistor 202 ON/OFF, dN 270 may switch transistor 210 ON/OFF, mN 114 may switch transistor 226 ON/OFF, and m 112 may switch transistor 246 ON/OFF. According to one or more embodiments, and as previously described above in relation to FIG. 2, when other conditions within the LPMSFF allow, mN 114 may connect to the supply voltage through transistor 202, m 112 may connect to the supply voltage through transistor 210, s 275 may connect to the ground through transistor 226, and s 280 may connect to the ground through transistor 246. In one or more embodiments, when a signal is connected to the supply voltage, it may be switched to a high value (1) regardless of its previous value, and when a signal is connected to the ground, it may be switched to a low value (0) regardless of its initial value. In one or more embodiments, D 105 may be a data input signal for the master latch circuit 110, and the complement of D 105, dN 270 may also serve as a data input signal for master latch circuit 110. The output signals from master latch circuit 110, m 112 and mN 114, may serve as data input signals for slave latch circuit 120. Therefore, in one or more embodiments, transistors (202, 210, 226, 246) may be data propagation transistors, because transistors (202, 210) may allow the data value of signals D 105 and dN 270 to be propagated to m 112 and/or mN114; and transistors (226, 246) may allow the data value of signals m 112 and mN 114 to be propagated to s 275 and/or sN 280.

In addition, FIG. 2 shows, according to one or more embodiments, that mN 114 may switch transistor 248 ON/OFF, m 112 may switch transistor 230 ON/OFF, s 275 may switch transistor 236 ON/OFF, and sN 280 may switch transistor 220 ON/OFF. In one or more embodiments mN 114 may be the complement of m 112, and sN 280 may be the complement of s 275. For example, when m 112 is equal to 1, mN 114 would be equal to 0, and vice-versa; and when s 275 is equal to 1, sN 280 would be equal to 0, and vice-versa. In one or more embodiments, if s 275 is equal to 1, then transistor 236 would be OFF, so that sN 280 may not connect to the supply voltage through transistor 236. In one or more embodiments, if s 275 is equal to 0, then, if other conditions within the LPMSFF allow, as described in aforementioned embodiments, then sN 280 may connect to the supply voltage through transistor 236. Thus, if s 275 is initially 0, then transistor 236 may allow sN 280 to be 1; or, if s 275 is initially 1, then transistor 236 may allow sN 280 to be 0. Therefore, in one or more embodiments, transistor 236 may help to maintain the complementary relationship between s 275 and sN 280, and help to retain the initial values of s 275 and sN 280. In one or more embodiments, if sN 280 is equal to 1, then transistor 220 would be OFF, so that s 275 may not connect to the supply voltage through transistor 220. In one or more embodiments if sN 280 is initially equal to 0, then, if other conditions within the LPMSFF allow, as described in aforementioned embodiments, then s 275 may connect to supply voltage through transistor 220. Thus, if sN 280 is initially 0, then transistor 220 may allow s 275 to be 1; or, if sN 280 is initially 1, then transistor 220 may allow s 275 to be 0. Therefore, in one or more embodiments, transistor 220 may help to maintain the complementary relationship between s 275 and sN 280, and help to retain the initial values of s 275 and sN 280.

FIG. 2 further shows, according to one or more embodiments, that if mN 114 is equal to 0, then transistor 248 would be OFF, and thus m 112 may not connect to the ground through transistor 248. If, however, mN 114 is equal to 1, then transistor 248 would be ON, and if other conditions within the LPMSFF allow, as previously described, then m 112 may connect to the ground through transistor 248. Thus, if mN 114 is initially 0, transistor 248 may allow m 112 to be equal to 1; or, if mN 114 is initially 1, transistor 248 may allow m 112 to be 0. Therefore, in one or more embodiments, transistor 248 may help to maintain the complementary relationship between m 112 and mN 114, and help to retain the initial values of m 112 and mN 114. In one or more embodiments, if m 112 is equal to 0, then transistor 230 would be OFF, and thus mN 114 may not connect to the ground through transistor 230. If, however, m 112 is equal to 1, then transistor 230 would be ON, and if other conditions within the LPMSFF allow, as previously described, then mN 114 may connect to the ground through transistor 230. Thus, if m 112 is initially 0, transistor 230 may allow mN 114 to be equal to 1; or, if m 112 is initially 1, transistor 220 may allow mN 114 to be equal to 0. Therefore, in one or more embodiments, transistor 230 may help to maintain the complementary relationship between m 112 and mN 114, and help to retain the initial values of m 112 and mN 114.

Therefore, in one or more embodiments, as shown by FIG. 2, transistors (230, 248) may assist in retaining the initial value of mN 114 and m 112; and transistors (220, 236) may assist in retaining the initial value of s 275 and sN 280. In one or more embodiments, due to their assistance in retaining the initial values of m 112, mN 114, s 275, and sN 280; transistors (230, 248, 220, 236) may be keeper transistors.

FIG. 2 also shows, according to one or more embodiments, that transistors (210, 220, 226) may connect to the supply voltage through clocked transistor 218. In one or more embodiments transistors (202, 236, 246) may connect to the supply voltage through clocked transistor 234. In one or more embodiments, transistors (220, 226, 230) may connect to the ground through clocked transistor 232. In one or more embodiments, transistors (236, 246, 248) may connect to ground through clocked transistor 250. Therefore, according to one or more embodiments, keeper transistors (230, 248, 220, 236) and data propagation transistors (202, 210, 226, 246) may share access to clocked transistors (218, 234, 232, 250) in such a manner that does not create functional issues by shorting nodes that may have opposite values. The aforementioned avoidance of the shorting of nodes that may have opposite values, according to one or more embodiments, in addition to other aspects of other embodiments described herein, may allow the sharing of clocked nodes to be robust and functionally non-disruptive. Also, in one or more embodiments, transistors (202, 210, 230, 248) in the master latch circuit 110 may share access to clocked transistors (218, 234, 232, 250) with transistors (220, 226, 236, 246) in the slave latch circuit 120. In one or more embodiments, sharing the clocked transistors (218, 234, 232, 250) in the aforementioned manner may reduce the total number of clocked transistors required, and thus reduce any power loss due to parasitic capacitance of clocked transistors.

FIG. 2 also shows, according one or more embodiments, that transistor 230 may be switched ON/OFF by m 112, and that transistor 226 may be switched ON/OFF by mN 114. In one or more embodiments, because mN 114 is the complement of m 112, transistor 226 and transistor 230 may not both be ON at the same time. In one or more embodiments, transistor 246 may be switched ON/OFF by m 112, and transistor 248 may be switched ON/OFF by mN 114. In one or more embodiments, because mN 114 is the complement of m 112, transistor 246 and transistor 248 may not both be ON at the same time.

FIG. 2 further shows, according to one or more embodiments, that if CP 130 is equal to 1, and sN 280 is equal to 0, and then dN 270 goes to 0, there may be a path from s 275 to m 112 through transistors (220, 210); however, because s 275 would be set equal to m 112 when CP 130 is equal to 1, the possible path through transistors (220, 210) would not cause the value of s 275 or m 112 to change, because the path through transistors (220, 210) would be connecting s 275 and m 112, which would already be equal.

FIG. 3 shows, according to one or more embodiments, a low power master-slave flip-flop (LPMSFF), having, in addition to the transistors of the embodiment shown in FIG. 2, two additional un-clocked pull-up PMOS transistors (302, 304), and removing from the embodiment of FIG. 2 the four un-clocked pull-up transistors (220, 236, 222, 240). In one or more embodiments, transistor 304 as shown in FIG. 3 may serve a similar function as transistor 222 (not shown), transistor 222 being previously shown in FIG. 2. In one or more embodiments, transistor 304 may be switched between ON and OFF states by the value of mN 114. If mN 114 is equal to 0, then transistor 304 would be ON. If other conditions within the LPMSFF allow transistor 224 to also be ON, in accordance with embodiments previously described in relation to FIG. 2, then s 275 may connect to supply voltage through transistors (224, 304). If mN 114 is equal to 1, then transistor 304 would be OFF, and so prevent a potential connection by s 275 to supply voltage through transistor 304.

In one or more embodiments, transistor 302, as shown in FIG. 3, may serve a similar function as transistor 240 (not shown), transistor 240 being previously shown in FIG. 2. In one or more embodiments, transistor 302 may be switched between ON and OFF states by the value of m 112. If m 112 is equal to 0, then transistor 302 would be ON. If other conditions within the LPMSFF allow, in accordance with embodiments previously described in relation to FIG. 2, transistor 242 to also be ON, then sN 280 may connect to supply voltage through transistors (242, 302). If m 112 is equal to 1, then transistor 302 would be OFF, and so prevent a potential connection by sN 280 to supply voltage through transistor 302.

FIG. 3 also shows, according to one or more embodiments, transistor 304 in parallel to transistor 218; and transistor 302 in parallel to transistor 234. In one or more embodiments, having transistor 304 in parallel to transistor 218 may allow the function of transistors (220, 224), as previously shown in FIG. 2, to be combined into a single transistor 224. In one or more embodiments, having transistor 302 in parallel to transistor 234 may allow the function of transistors (236, 242), as previously shown in FIG. 2, to be combined into a single transistor 242. Thus, an embodiment as shown in FIG. 3 may reduce by two, by removal of transistors (220, 236), the number of transistors required below that required of an embodiment as shown in FIG. 2.

FIG. 3 also shows, according to one or more embodiments, alternate connections for transistors (230, 248), as compared to the one or more embodiments shown by FIG. 2. In one or more embodiments, as shown in FIG. 3, the drain node of transistor 230 may be connected to a node dg0 310, instead of being connected to the node cpg0 294 as previously shown in FIG. 2. In one or more embodiments, as shown in FIG. 3, the drain node of transistor 248 may be connected to a node dg1 315, instead of being connected to the node cpg1 296 as previously shown in FIG. 2. The alternate connections of transistors (230, 248) as shown in FIG. 3, as opposed to the connections for transistors (230, 248) as previously shown in FIG. 2, may reduce any leakage which might occur at the nodes m 112 and/or mN 114, by reducing the number of NMOS transistors directly connected to each of those nodes from two as previously shown in FIG. 2, to one as shown in FIG. 3. Leakage may occur in a circuit when a small amount of current flows through a transistor, or other circuit element, even though the transistor or other circuit element is switched OFF. For example, if m 112 were equal to 0, its complement mN 114 would be equal to 1, and thus transistor 212 would be OFF. However, due to leakage, transistor 212 might allow a small amount of current to flow from the supply voltage through transistor 212 to m 112. In another example, if mN 114 were equal to 0, m 112, being the complement of mN 114, would be equal to 1, and thus transistor 204 would be OFF. However, due to leakage, transistor 214 might allow a small amount of current to flow from the supply voltage through transistor 204 to mN 114.

FIG. 4 shows, according to one or more embodiments, a low power master-slave flip-flop, in which transistors (230, 248), which were previously shown in FIG. 2 and FIG. 3, have been removed. In one or more embodiments, according to FIG. 4, transistors (232, 250) no longer have a direct connection to ground as previously shown in FIG. 2 and FIG. 3. Transistor 232 may, as shown in FIG. 4, allow a connection to ground through the node dg0 310 and transistor 216, if other conditions in the LPMSFF allow transistor 216 to be ON, as described in previous embodiments. Transistor 250 may, as shown in FIG. 4, allow a connection to ground through node dg1 315 and transistor 208, if other conditions in the LPMSFF allow transistor 208 to be ON, as described in aforementioned embodiments.

FIG. 4 also shows, according to one or more embodiments, that, if CP 130 is equal to 1, after s 275 has been set equal to m 112, and sN 280 has been set equal to mN 114, consistent with aforementioned embodiments, even if the value of D 105 changes, a path through transistors (226, 232, 214) would be maintained to keep m 112 equal to 0 if s 275 is equal to 0; and/or a path through transistors (246, 250, 206) would be maintained to keep mN 114 equal to sN 280, if sN 280 is equal to 0.

FIG. 5 shows, according to one or more embodiments, a process flow diagram detailing the operations of providing a low power master-slave flip-flop 100. In one or more embodiments, operation 502 may involve providing a clocked pull-up component 102 comprising a first clock gated transistor 234 and a second clock gated transistor 218, as illustrated in FIGS. 2, 3 and 4 respectively. In one or more embodiments, operation 504 may involve providing a master latch component 110 configured to propagate a true level of an embedded logic function of a data input bundle D 605 to a master true storage node m 112, and a complement level of the embedded logic function of the input data bundle D 605 to a master complement storage node 114 when a clock signal CP 130 is at a first level; and to hold a first value of the master true storage node m 112 and hold a second value of the master complement storage node mN 114 constant when a clock signal CP 130 is at a second level, and the master latch component 110 comprises a complement pull-up logic cone 602 configured to generate a complement level of the embedded logic function of the data input bundle D 605, coupled between the first clock gated transistor 234 and the master complement storage node mN 114, and a true pull-up logic cone 610 configured to generate a true level of the embedded logic function of the data input bundle D 605, coupled between the second clock gated transistor 218 and the master true storage node m 112. In one or more embodiments, operation 506 may involve providing a slave latch component 120 having a slave true storage node s 275 and a slave complement storage node sN 280 with the slave true storage node s 275 communicatively coupled to the master true storage node m 112 when the clock signal CP 130 is at the second level, so that a value of the true storage node s 275 is set equal to the value of the master storage true node m 112, and decoupled when the clock signal CP 130 is at the first level, so that the slave true storage node s 275 retains a previous value, and with the slave complement storage node sN 280 communicatively coupled to the master complement storage node mN 114 when the clock signal CP 130 is at the second level, so that a value of the slave complement storage node sN 280 is set equal to the value of the master complement storage node mN 114, and decoupled when the clock signal CP 130 is at the first level, so that the slave complement storage node retains a previous value; comprising a transistor 236 gated by the slave true storage node s 275 and coupled between the first clock gated transistor 234 and the slave complement storage node sN 280; and a transistor gated by the slave complement storage node sN 280, coupled between the second clock gated transistor 218 and the slave true storage node s 275.

FIG. 6 shows, according to one or more embodiments, a low power master-slave flip-flop with embedded logic comprising a complement pull-up logic cone 602, a true pull-up logic cone 610, a complement pull-down logic cone 608, and a true pull-down logic cone 616, and input bundle D 605, containing multiple input signals. In one or more embodiments, complement pull-up logic cone 602, true pull-up logic cone 610, complement pull-down logic cone 608, and/or true pull-down logic cone 616, may comprise one or more embedded logic functions. In one or more embodiments, input bundle D 605 may comprise a single signal, such as input signal D 105, as shown in previously described embodiments. In one or more embodiments, complement pull-up logic cone 602 and true pull-up logic cone 610 may allow connections to the source voltage when enabled. In one or more embodiments, complement pull-down logic cone 608 and true pull-down logic cone 616 may allow connections to the ground when enabled. In one or more embodiments, the complement pull-up logic cone 602 and the complement pull-down logic cone 608 may be configured to propagate a low value to master complement storage node mN 114 when input bundle D 605 satisfies a desired embedded logic function, and a high value otherwise. In one or more embodiments the true pull-up logic cone 610 and the true pull-down logic cone 616 may be configured to propagate a high value to master true storage node m 112 when input bundle D 605 satisfies the aforementioned embedded logic function, and a low value otherwise. For example, complement pull-up logic cone 602 may consist of parallel PMOS transistors and complement pull-down logic cone 608 may consist of series NMOS transistors gated by true values of signals in input bundle D 605 in order to propagate a low value to master complement storage node mN 114 when all signals in input bundle D 605 have a high value, and propagate a high value otherwise. True pull-up logic cone 610 may further consist of series PMOS transistors and true pull-down logic cone 616 may consist of parallel NMOS transistors gated by complement values of signals in input bundle D 605 in order to propagate a high value to master true storage node m 112 when all signals in input bundle D 605 have a high value, and propagate a low value otherwise. Such a configuration would allow for a logical AND function to be embedded in the flip-flop. In other embodiments, the input logic 650 may comprise one or more embedded logic functions, such as an inverter, configured to generate intermediate data signal bundles T 618 and C 620, to control the true and complement logic cones. In one or more embodiments, the complement pull-up logic cone 602 may be configured to disallow a connection to the power supply through transistor 234 when input bundle D 605 satisfies a desired embedded logic function, and allow otherwise. In one or more embodiments, the true pull-up logic cone 610 may be configured to allow a connection to the power supply through transistor 218 when input bundle D 605 has a value that satisfies the aforementioned embedded logic function, and disallow otherwise. In one or more embodiments, the complement pull-down logic cone 608 may be configured to allow a connection to ground when input bundle D 605 satisfies a desired embedded logic function, and disallow otherwise. In one or more embodiments, the true pull-down logic cone 616 may be configured to disallow a connection to the ground when input bundle D605 satisfies the aforementioned desired embedded logic function, and allow otherwise.

Although the present embodiments have been described with reference to specific example embodiments, it would be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. For example, the various devices and modules described herein may be enabled and operated using hardware circuitry (e.g., CMOS based logic circuitry), firmware, software or any combination of hardware, firmware, and software (e.g., embodied in a non-transitory machine-readable medium). For example, the various electrical structure and methods may be embodied using transistors, logic gates, and electrical circuits (e.g., application specific integrated (ASIC) circuitry and/or Digital Signal Processor (DSP) circuitry).

In addition, it would be appreciated that the various operations, processes and methods disclosed herein may be embodied in a non-transitory machine-readable medium and/or a machine-accessible medium compatible with a data processing system (e.g., a computer system), and/or may be performed in any order. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

A number of embodiments have been described. Nevertheless, it would be understood that various modifications may be made without departing from the spirit and scope of the claimed invention. In addition, the logic flows depicted in the figures do not require the particular order shown, or sequential order, to achieve desirable results. In addition, other steps may be provided, or steps may be eliminated, from the described flows, and other components may be added to, or removed from, the described systems. Accordingly, other embodiments are within the scope of the following claims.

The structures and modules in the figures may be shown as distinct and communicating with only a few specific structures and not others. The structures may be merged with each other, may perform overlapping functions, and may communicate with other structures not shown to be connected in the figures. Accordingly, the specification and/or drawings may be regarded in an illustrative rather than a restrictive sense. 

What is claimed is:
 1. A flip-flop circuit comprising: a clocked pull-up component comprising: a first clock gated pull-up transistor, coupled to a supply voltage, and a second clock gated pull-up transistor, coupled to the supply voltage; a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node when a clock signal is at a first level; and to hold a first value of the master true storage node and hold a second value of the master complement storage node constant when a clock signal is at a second level; comprising: a complement pull-up logic cone configured to generate the complement level of the embedded logic function of the data input bundle, coupled between the first clock gated pull-up transistor and the master complement storage node, and a true pull-up logic cone configured to generate the true level of the embedded logic function of the data input bundle, coupled between the second clock gated pull-up transistor and the master true storage node; and a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value, and with the slave complement storage node communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock signal is at the first level, so that the slave complement storage node retains a previous value; comprising: a transistor gated by the slave true storage node, coupled between the first clock gated pull-up transistor and the slave complement storage node, and a transistor gated by the slave complement storage node, coupled between the second clock gated pull-up transistor and the slave true storage node.
 2. The flip-flop circuit of claim 1, wherein the complement pull-up logic cone is a transistor gated by a true value of a data input; and the true pull-up logic cone is a transistor gated by the complement value of the data input.
 3. The flip-flop circuit of claim 1, further comprising: a transistor gated by the master true storage node, coupled in parallel with the first clock gated pull-up transistor; and a transistor gated by the master complement storage node, coupled in parallel with the second clock gated pull-up transistor.
 4. The flip-flop circuit of claim 1, wherein the master latch component further comprises: a transistor gated by the master true storage node and coupled between a supply voltage and the master complement storage node; a transistor gated by the master complement storage node and coupled between the supply voltage and the master true storage node; a transistor gated by the master true storage node, and the complement pull-up logic cone, coupled in series between a ground and the master complement storage node; and a transistor gated by the master complement storage node, and the true pull-up logic cone, coupled in series between the ground and the master true storage node.
 5. The flip-flop circuit of claim 1, wherein the slave latch component further comprises: a transistor gated by the slave true storage node and coupled between a ground and the slave complement storage node; a transistor gated by the slave complement storage node and coupled between the ground and the slave true storage node; a transistor gated by the slave true storage node, and a transistor gated by the master true storage node, coupled in series between a supply voltage and the slave complement storage node; and a transistor gated by the slave complement storage node, and a transistor gated by the master complement storage node, coupled in series between the supply voltage and the slave true storage node.
 6. The flip-flop circuit of claim 1, further comprising: a clocked pull-down component comprising: a first clock gated pull-down transistor, coupled to a ground, and a second clock gated pull-down transistor, coupled to the ground; wherein the master latch component further comprises: a transistor gated by the master true storage node coupled between the first clock gated pull-down transistor and the master complement storage node, and a transistor gated by the master complement storage node coupled between the second clock gated pull-down transistor and the master true storage node; and wherein the slave latch component further comprises: a transistor gated by the master complement storage node coupled between the first clock gated pull-down transistor and the slave true storage node, and a transistor gated by the master true storage node coupled between the second clock gated pull-down transistor and the slave complement storage node.
 7. The flip-flop circuit of claim 1, wherein the master latch component further comprises: a complement pull-down logic cone, configured to generate the complement level of the embedded logic function of the data input bundle, coupled to a ground and to a transistor gated by the master true storage node also coupled to master complement storage node; and a true pull-down logic cone, configured to generate the true level of the embedded logic function of the data input bundle, coupled to a ground and to a transistor gated by the master complement storage node also coupled to master true storage node.
 8. The flip-flop circuit of claim 7, wherein the complement pull-up logic cone is a transistor gated by a true value of a data input; and the true pull-up logic cone is a transistor gated by the complement value of a data input.
 9. The flip-flop circuit of claim 7, further comprising: a clocked pull-down component comprising: a first clock gated pull-down transistor coupled to a ground, and a second clock gated pull-down transistor coupled to the ground; wherein the master latch component further comprises: a transistor gated by the master true storage node coupled between the first clock gated pull-down transistor and the complement pull-down logic cone; and a transistor gated by the master complement storage node coupled between the second clock gated pull-down transistor and the true pull-down logic cone; and wherein the slave latch component further comprises: a transistor gated by the master complement storage node coupled between the first clock gated pull-down transistor and the slave true storage node, a transistor gated by the master true storage node coupled between the second clock gated pull-down transistor and the slave complement storage node.
 10. The flip-flop circuit of claim 7, further comprising: a first pull-down transistor gated by the clock signal, and a second transistor gated by the master true storage node; the first transistor and second transistor coupled in series between the complement pull-down logic cone and the slave complement storage node; and a third pull-down transistor gated by the clock signal, and a fourth transistor gated by the master complement storage node, the third transistor and the fourth transistor coupled in series between the true pull-down logic cone and the slave true storage node.
 11. A flip-flop circuit comprising: a clocked pull-down component comprising: a first clock gated pull-down transistor, coupled to a ground voltage, and a second clock gated pull-down transistor, coupled to the ground voltage; a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement storage node when a clock signal is at a first level; and to hold a first value of the master true storage node and hold a second value of the master complement storage node constant when the clock signal is at a second level; comprising: a complement pull-down logic cone configured to generate the complement level of the embedded logic function of the data input bundle, coupled between the first clock gated pull-down transistor and the master complement storage node, and a true pull-down logic cone configured to generate the true level of the embedded logic function of the data input bundle, coupled between the second clock gated pull-down transistor and the master true storage node; and a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal is at the first level, so that the slave true storage node retains a previous value, and with the slave complement storage node communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled when the clock signal is at the first level, so that the slave complement storage node retains a previous value; comprising: a transistor gated by the slave true storage node, coupled between the first clock gated pull-down transistor and the slave complement storage node, and a transistor gated by the slave complement storage node, coupled between the second clock gated pull-down transistor and the slave true storage node.
 12. The flip-flop circuit of claim 11, wherein the complement pull-down logic cone is a transistor gated by a true value of a data input; and the true pull-down logic cone is a transistor gated by the complement value of a data input.
 13. The flip-flop circuit of claim 11, further comprising: a transistor gated by the master true storage node, coupled in parallel with the first clock gated pull-down transistor; and a transistor gated by the master complement storage node, coupled in parallel with the second clock gated pull-down transistor.
 14. The flip-flop circuit of claim 11, wherein the master latch component further comprises: a transistor gated by the master true storage node and coupled between the ground voltage and the master complement storage node; a transistor gated by the master complement storage node and coupled between the ground voltage and the master true storage node; a transistor gated by the master true storage node, and the complement pull-down logic cone, coupled in series between a supply and the master complement storage node; and a transistor gated by the master complement storage node, and the true pull-down logic cone, coupled in series between the supply and the master true storage node.
 15. The flip-flop circuit of claim 11, wherein the slave latch component further comprises: a transistor gated by the slave true storage node and coupled between a supply and the slave complement storage node; a transistor gated by the slave complement storage node and coupled between the supply and the slave true storage node; a transistor gated by the slave true storage node, and a transistor gated by the master true storage node, coupled in series between the ground voltage and the slave complement storage node; and a transistor gated by the slave complement storage node, and a transistor gated by the master complement storage node, coupled in series between the ground voltage and the slave true storage node.
 16. The flip-flop circuit of claim 11, further comprising: a clocked pull-up component comprising: a first clock gated pull-up transistor, coupled to a supply, and a second clock gated pull-up transistor, coupled to the supply; wherein the master latch component further comprises: a transistor gated by the master true storage node coupled between the first clock gated pull-up transistor and the master complement storage node, and a transistor gated by the master complement storage node coupled between the second clock gated pull-up transistor and the master true storage node; and wherein the slave latch component further comprises: a transistor gated by the master complement storage node coupled between the first clock gated pull-up transistor and the slave true storage node, and a transistor gated by the master true storage node coupled between the second clock gated pull-up transistor and the slave complement storage node.
 17. The flip-flop circuit of claim 11, wherein the master latch component further comprises: a complement pull-up logic cone, configured to generate the complement level of the embedded logic function of the data input bundle, coupled to a supply and to a transistor gated by the master true storage node also coupled to master complement storage node; and a true pull-up logic cone, configured to generate the true level of the embedded logic function of the data input bundle, coupled to the supply and to a transistor gated by the master complement storage node also coupled to master true storage node.
 18. The flip-flop circuit of claim 17, wherein the complement pull-down logic cone is a transistor gated by a true value of a data input; and the true pull-down logic cone is a transistor gated by the complement value of a data input.
 19. The flip-flop circuit of claim 17, further comprising: a clocked pull-up component comprising: a first clock gated pull-up transistor coupled to the supply, and a second clock gated pull-up transistor coupled to the supply; wherein the master latch component further comprises: a transistor gated by the master true storage node coupled between the first clock gated pull-up transistor and the complement pull-up logic cone; and a transistor gated by the master complement storage node coupled between the second clock gated pull-up transistor and the true pull-up logic cone; and wherein the slave latch component further comprises: a transistor gated by the master complement storage node coupled between the first clock gated pull-up transistor and the slave true storage node, a transistor gated by the master true storage node coupled between the second clock gated pull-up transistor and the slave complement storage node.
 20. The flip-flop circuit of claim 17, further comprising: a first pull-up transistor gated by the clock signal, and a second transistor gated by the master true storage node; the first transistor and second transistor coupled in series between the complement pull-up logic cone and the slave complement storage node; and a third pull-up transistor gated by the clock signal, and a fourth transistor gated by the master complement storage node, the third transistor and the fourth transistor coupled in series between the true pull-up logic cone and the slave true storage node. 